SC427MLTRT【PDF 21/33 页】IC REG DL BUCK/LINEAR 32MLPQ

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SC417/SC427

Power Good Output

The power good (PGOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage

is 10% below the nominal voltage, PGOOD is pulled low. It

is held low until the output voltage returns above -8% of

nominal. PGOOD is held low during start-up and will not

be allowed to transition high until soft-start is completed

(when V

reaches 500mV) and typically 2ms has passed.

PGOOD will transition low if the V

pin exceeds +20% of

nominal, which is also the over-voltage shutdown thresh-

old (600mV). PGOOD also pulls low if the EN/PSV pin is

low when V5V is present.

Output Over-Voltage Protection

Over-voltage protection becomes active as soon as the

device is enabled. The threshold is set at 500mV + 20%

(600mV). When V

exceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off, until the EN/PSV input

is toggled or V5V is cycled. There is a 5約 delay built into

the OVP detector to prevent false transitions. PGOOD is

also low after an OVP event.

Output Under-Voltage Protection

When V

falls 25% below its nominal voltage (falls to

375mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tri-

state the MOSFETs. The controller stays off until EN/PSV is

toggled or V5V is cycled.

V5V UVLO, and POR

Under-Voltage Lock-Out (UVLO) circuitry inhibits switching

and tri-states the DH/DL drivers until V5V rises above 3.9V.

An internal Power-On Reset (POR) occurs when V5V exceeds

3.9V, which resets the fault latch and soft-start counter to

prepare for soft-start. The SC417/SC427 then begins a soft-

start cycle. The PWM will shut off if V5V falls below 3.6V.

LDO Regulator

The LDO output is programmable from 0.75V to 5.25V

using external resistors. The feedback pin (FBL) for the

LDO is regulated to 750mV. There is also an enable pin

(ENL) for the LDO that provides independent control. The

LDO voltage can also be used to provide the bias voltage

for the switching regulator. When a separate source is

used as the bias supply, the LDO can be programmed to

provide a different voltage (see Figure 9).

VLDO

To FBL pin

LDO2

LDO1

Figure 9 LDO Start-Up

The LDO output voltage is set by the following equation.

LDO

750

VLDO

A minimum capacitance of 1糉 referenced to AGND is

normally required at the output of the LDO for stability. If

the LDO is providing bias power to the device, then a

minimum 0.1糉 capacitor referenced to AGND is required

along with a minimum 1.0糉 capacitor referenced to

PGND to filter the gate drive pulses. Refer to the layout

guidelines section.

LDO ENL Functions

The ENL input is used to enable/disable the internal LDO.

When ENL is a logic low, the LDO is off. When ENL is a high

but below the VIN UVLO threshold (2.6V typical), then the

LDO is on and the switcher is off. When ENL is above the V

UVLO threshold, the LDO is enabled and the switcher is also

enabled if the EN/PSV pin is not grounded. The table below

summarizes the function of ENL and EN/PSV pins.

EN/PSV

ENL

LDO Switcher

Disabled Low, < 0.4V OFF OFF

Enabled Low, < 0.4V OFF ON

Disabled 1.0V < High < 2.6V ON OFF

Enabled 1.0V < High < 2.6V ON OFF

Disabled High, > 2.6V ON OFF

Enabled High, > 2.6V ON ON

The ENL pin also acts as the switcher under-voltage lockout

for the V

supply. When SC417/SC427 is self-biased from

the LDO and runs from the V

power source only, the VIN

UVLO feature can be used to prevent false UV faults for the

PWM output by programming with a resistor divider at the

VIN, ENL and AGND pins. When SC417/SC427 has an exter-

Applications Information (continued)

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